gate-level

Open-source, gate-level testing and general verification tools would be a great investment in that they reduce this significantly.

This is usually used to compare the Verilog RTL to the gate-level netlist as an additional quality control measure.

Decent optical microscope is more than adequate for photos like that; electron microscope is for gate-level.

So Chisel seems worse than MyHDL but neither can support verifying a gate-level sim so you are somewhat screwed either way.

Essentially once you translate your Chisel design to verilog you basically can't reuse your verification environment for the RTL simulation or the gate-level.

If that stuff is written in Chisel so it can be simulated by the C++, then you are screwed for the RTL and gate-level.

Switch-level simulation can provide more accurate timing predictions than gate-level simulation, but without the ability to use logic-cell delays as parameters of the models.

They run Verilog simulation on RTL and gate-level using Synopsys VCS.

MyHDL is talking about co-simulation on the gate-level netlist.

We won't have good numbers until we have gate-level sims of the hierarchy, so for now all there is to go on is skill and expertise.

It's easy for us, already fully immersed, to say that beginners should or would be interested to know all of the logic gate-level mechanisms, but it's going to be off-putting for most.

I am fantasizing if its possible to also write the Verification IP in Chisel AND convert that into a separate c++ library, then you can reuse it in a commercial Verilog RTL and gate-level simulator via a PLI.