netlist

The output is called a netlist is more of a mathematical construct of connections over perfect wires (everything is ideal i.e.

This step should also detect repeated gate mpatterns in the netlist and de-duplicate them (This is crazy important since it can shrink a netlist substantially).

This is usually used to compare the Verilog RTL to the gate-level netlist as an additional quality control measure.

On the other hand, the schematic requires no graphical representation and is easily written as a netlist.

Synthesis is the process of taking higher level hardware descriptions and outputing the lower level descriptions usually called a netlist.

One can even Cosimulation with the back-annotated layout netlist and verify - yes cycle accurate.

And we have to write the processor code in a hardware/netlist language that we have to design ourselves.

Once you have some nice clean scans which align properly, there exist programs[0] which will turn it into a netlist for you.

There's netlist files for schematics, but they're a bit raw to do by hand...

And we have to write ourselves the interpreter we will use for that netlist language.

Sure, it'd be nice to have open drivers, but so would having the RTL of the processor, and the netlist and gerber of the board.

In principle what you're asking is simple - you pass in the netlist and manually place important components and then let the autorouter do the rest.