myhdl

The Verilog RTL parts run in the Verilog simulator while the MyHDL parts run in the MyHDL simulator.

I would suggest using myhdl (www.myhdl.org), and then plugging the verilog/vhdl it generates into your vendor's tools.

Anyone can verify this themselves by creating an RTL description in MyHDL, convert it to Verilog, and perform a Cosimulation.

So Chisel seems worse than MyHDL but neither can support verifying a gate-level sim so you are somewhat screwed either way.

The ability to mix the MyHDL designs and Verilog RTL designs into one simulation.

This is ridiculous, you can create cycle accurate (and bit accurate) descriptions in MyHDL.

Are you referring to a new DSL based on software languages, something like MyHDL?

So if you had a 3rd party mem cache in Verilog you could connect it to your MyHDL CPU and run a simulation.

They're not perfect but I thought that MyHDL feature was a knockoff of what industry was already doing haha.

But for me it's a good surprise that MyHDL manages to knockoff that feature because the other HLS don't seem to be able to.

This is where the cosimulation that MyHDL supports is so handy.

However they say MyHDL can do co-simulation on Verilog RTL.

The biggest problem with MyHDL in my opinion (As someone using Chisel to make a commercial processor) is its (non existent) "real" simulation capabilities.

"This is where the cosimulation that MyHDL supports is so handy." All this time, I thought co-simulation (i.e.

In my opinion, Chisel feels like "lets write Verilog with Scala syntax." I personally see MyHDL as a better approach as you can leverage existing libraries for generating code (i.e.