(computer languages, hardware) A language used to design and model electronic circuits
Used in a Sentence
verilog
Definition, parts of speech, synonyms, and sentence examples for verilog.
Editorial note
The Verilog RTL parts run in the Verilog simulator while the MyHDL parts run in the MyHDL simulator.
Examples19
Definitions1
Parts of speech1
Quick take
(computer languages, hardware) A language used to design and model electronic circuits
Meaning at a glance
The clearest senses and uses of verilog gathered in one view.
Definitions
Core meanings and parts of speech for verilog.
noun
(computer languages, hardware) A language used to design and model electronic circuits
Example sentences
The Verilog RTL parts run in the Verilog simulator while the MyHDL parts run in the MyHDL simulator.
This is usually used to compare the Verilog RTL to the gate-level netlist as an additional quality control measure.
(Note: There is a big difference between generated verilog, in the Chisel sense, and synthesized verilog, in the MyHDL sense).
How do they test that the Chisel RTL and the generated Verilog are equivalent though?
The ability to mix the MyHDL designs and Verilog RTL designs into one simulation.
Feel free to ask any Verilog question or point any rule I missed (I'm sure there are many).
And now you are saying you don't test on the generated Verilog from Chisel?
So if you had a 3rd party mem cache in Verilog you could connect it to your MyHDL CPU and run a simulation.
Maybe there's a tool here or there that generates a little Verilog from some other language for you but that is very piecemeal.
Essentially once you translate your Chisel design to verilog you basically can't reuse your verification environment for the RTL simulation or the gate-level.
Or you run some sub-modules of the design in a Verilog simulator and other sub-modules in your HLS tool simulator and the modules can interact.
They run Verilog simulation on RTL and gate-level using Synopsys VCS.
Quote examples
There's probably no Chisel-Verilog FEC or "any HLS"-Verilog FEC tool!
No "translation" process happens, and thus you don't have any problem actually simulating at the same RTL level as Verilog.
This is useless without any data: "big difference between the generated verilog".
What you linked to there seems to be a "mode" (Can't think of a better name to describe it at the moment), similar to how you can embed verilog or C++ into Chisel.
Proper noun examples
Anyone can verify this themselves by creating an RTL description in MyHDL, convert it to Verilog, and perform a Cosimulation.
One plus is Chisel generates C++ code for testing your design which is a huge speed increase versus simulating Verilog.
What simulator do you use to test the generated Verilog?
Frequently asked questions
Short answers drawn from the clearest meanings and examples for this word.
How do you use verilog in a sentence?
The Verilog RTL parts run in the Verilog simulator while the MyHDL parts run in the MyHDL simulator.
What does verilog mean?
(computer languages, hardware) A language used to design and model electronic circuits
What part of speech is verilog?
verilog is commonly used as noun.