combinational

Combinational verification is quote easy, because modern SAT solvers can prove almost all combinational properties you can throw at them.

At best, the answer is combinational in the number of synaptic connections in certain parts of the brain.

But they can only be used to describe combinational logic.

It would be interesting to see what could be done with large scale combinational logic (ie.

If you look at how an integer is implemented in hardware (say in a register or in combinational logic), you're not going to find the bits being reversed every byte.

This thing also separates externally visible events recorded in the (infinite) list of values from externally unobservable pure (combinational) logic.

There is a chasm between synchronous logic (everything in a big switch/case) and combinational statements.

Since electronics no longer use combinational logic in discrete chips, no newer software is available.

Come on, you haven't even described how to implement combinational logic using 555 timer chips.

At the moment, only combinational circuits are possible, but I'm working to extend this to synchronous (clocked) circuits.

The Verilog rules—using non-blocking assignments for sequential logic and blocking assignments for combinational logic—fail as soon as the scenario becomes slightly complex.

You misunderstood the problem: It's not a problem that you can describe a latch, but that it's so easy to make the mistake of describing a latch instead of combinational logic.

The best "real engineers" do not "think directly" on how to solve the problem with registers and combinational logic.

One of the missing pieces is we don't know what the minimum set of combinational factors are to create "advanced" civilization.

I suspect that just having "Haskell" got the link a lot of upvotes:-) As stated on the "Why CλaSH", the advantage is obvious for combinational circuits.

This is what I use when I play with hardware simulation in Haskell: type S a = [a] register:: a -> S a -> S a register a0 as = a0:as -- combinational logic can be represented as typical pure -- functions and then glued into "circuits" with register's -- and map/zip/unzip functions.