superscalar

The CPU is happily looking ahead and decoding instructions, when one of the superscalar pipelines has a store into the instruction stream.

Assuming pretty cache-optimal code and 1.5GHz ops with no superscalar gains, that's over 25 million operations per record.

For example they could have used a Xilinx Zynq, which includes hard Cortex A9 cores, which are out-of-order and superscalar.

In fact, in a sense that's what superscalar CPUs have already been doing for decades.

Plus, most instructions are actually out-of-order on x86 (hence the out-of-order superscalar).

Modern CPUs are so superscalar internally that an overflow check (which doesn't get flagged most of the time anyway) doesn't add anything to the execution speed.

Then superscalar came to microprocessors with the Pentium Pro.

Hmm, but wasn't the PowerPC 601 superscalar?

That's true of all superscalar machines.

> Then superscalar came to microprocessors with the Pentium Pro.

>> Modern CPUs are so superscalar internally that an overflow check (which doesn't get flagged most of the time anyway) doesn't add anything to the execution speed.

> Modern CPUs are so superscalar internally that an overflow check (which doesn't get flagged most of the time anyway) doesn't add anything to the execution speed.

Does Mill CPU Architecture deal somehow with this besides the claimed "10x single-thread power/performance gain over conventional out-of-order superscalar architectures"¹?

These checks may cause expensive branch mispredictions or impair superscalar execution." They also discuss why this is so (specialized instructions in modern processors, and modern processors and superscaler allowing execution of multiple such operations per cycle).

> "a split organization increases the total number of registers accessible with a given instruction width, simplifies provision of enough regfile ports for wide superscalar issue, supports decoupled floating-point unit architectures, and simplifies use of internal floating-point encoding techniques.

IA64 had wide "bundles" for superscalar issue, but it explicitly avoided exposing the individual instructions as "ports" and instead had a more flexible setup where, really, the bundles contained "just a bunch of independent instructions".